The present disclosure relates, in general, to image sensors and, in particular, to silicon-on-insulator (SOI) active pixel sensors with the photosites implemented in the substrate.
In general, image sensors find applications in a wide variety of fields, including machine vision, robotics, guidance and navigation, and automotive applications, as well as consumer products. While complementary metal-oxide-semiconductor CMOS) technology has provided the foundation for advances in low-cost, low-power, reliable, highly integrated systems for many consumer applications, charge coupled devices (CCDs) have been, until recently, the primary technology used in electronic imaging applications. CCDs, however, are high capacitance devices that require high voltage clocks, consume large amounts of energy, and provide only serial output. They require specialized silicon processing that is not compatible with CMOS technology.
More recently, the availability of near or sub-micron CMOS technology and the advent of active pixel sensors (APS) have made CMOS technology more attractive for imaging applications. Active pixel sensors have one or more active transistors within the pixel unit cell and can be made compatible with CMOS technologies.
In the past few years, small pixel sizes, low noise, high speed, and high dynamic range have been achieved in CMOS imagers. In addition, a wide variety of pixel architectures and designs that optimize various aspects of imager performance have been demonstrated using CMOS-based technology.
It is expected that scaling of MOS devices to smaller geometries will continue to yield higher operating speeds and greater packing densities in CMOS-based integrated circuits. While fine geometries are desirable for computers and other circuits, such scaling can adversely affect the performance of imagers. For example, the scaling of MOS devices in imagers requires a continued increase in channel doping, thus leading to significantly reduced depletion widths on the order of less than 0.1 micron (μm).
As shown in FIG. 1, a photosite is implemented using bulk-CMOS technology. In this context, “bulk-CMOS” technology refers to the fact that the substrate 20 is an integral part of the MOS devices. The photo-collection site is the reverse-biased photodiode 22 formed by the n+/p-substrate junction 24. Photocarriers are stored at the n+/p interface where the potential is highest. Photoelectrons generated within the depletion region 26 are collected at the interface 24 with a high efficiency due to the existence of an electric field. On the other hand, only some of the photoelectrons generated outside the depletion region 26 will diffuse into the collecting area, thereby reducing the collection efficiency and increasing cross-talk.
For photons having a wavelength in the range of 400-800 nanometers (nm), the photon absorption depth varies from about 0.1 to 10 μm. However, in a typical 0.5 μm CMOS technology, the depletion widths are less than 0.2 μm. With the exception of blue light, many photons in the visible spectrum will be absorbed outside the depletion region 26. Therefore, CMOS imagers implemented using a 0.5 μm technology will exhibit a lower quantum efficiency and increased cross-talk compared to imagers implemented with a coarser process. The increased cross-talk can lead to degraded color performance and smear. In addition to optical cross-talk, imagers made using bulk-CMOS technology also tend to exhibit electrical cross-talk.
Another problem in imagers made using bulk-CMOS technology is a rise in photodiode leakage current when the device is exposed to radiation. The rise in leakage current is caused by the use of Local Oxidation of Silicon (LOCOS) processes to create isolation regions 28 between active circuits. The “bird's beak” 30 feature at the transition between the thin-gate oxide region 32 and the thick field-oxide region creates a high electric field, thereby causing increased trap-generation during exposure to radiation. Although the leakage current can be reduced by using a radiation-hard fabrication process, such processes are relatively expensive and add to the overall cost of the imager.
In contrast to bulk-CMOS technology, SOI-CMOS technologies have recently been developed. In a SOI-CMOS process, a thick silicon substrate is separated from a thin silicon film by a buried oxide. The thin silicon film is patterned to produce the MOS devices. The principal of operation is similar to the operation of bulk-MOS devices, except the transistors do not share a common substrate.
The thin-film nature of SOI-MOS devices and the absence of a common substrate can provide several advantages over bulk-MOS devices, including better performance for short channel devices, lower power and higher speed resulting from lower parasitic capacitance, and no latch-up. In addition, SOI-CMOS processes can provide higher device density, less leakage current and radiation hardness.
Nevertheless, the thin silicon film in SOI-MOS devices previously has made them unsuitable for imagers. In particular, the silicon film, with a thickness of only about 0.1-0.3 μm, is too thin to efficiently absorb visible light with photon depths of about 3-4 μm.